DC Load – #1

My home lab could definitively benefit from an electronic dummy load (EDL). I have a couple of projects on the way for which I could use one for testing purposes. One of these projects is a linear power supply, and I am sure most of you people know that hacking together something to simulate a half decent load only gets you so far. In addition, I have a plan to design a portable LiFePO4 power pack for my telescope mount where an EDL would come in very handy for testing purposes.

Google tells me that designing your own EDL is a common project for a hobbyist EE, so this should definitively be doable.

Let’s get this show on the road!

Specifications

Since this is my first “real” EE project, I’d like to do it by the books. I learned in the past that it is very easy to get lost in the details while trying to design an electronic circuit (feature creep, anyone?) and so we’ll start by laying out the specs of the gadget we’re trying to build.

One of the reasons I am building this load is to test an upcoming PSU. This means that it will have to cope with its maximum power output: 30 volts at five amps (150 watts).

Resolution should be in the milliamps range, preferably over the whole range of the load. Obviously, current draw should be as stable as possible and transient response must not be too abysmal. Obviously faster is better but since this is still a hobbyist project we’ll say that anything in the single-digit millisecond range will do.

At maximum, the EDL will need to sink 150 watts of power. Since all of this will have to be transformed into heat, thermal management is going to be an issue. I am not a huge fan of fans (see what I did there?) but I seriously doubt that we can go passively cooled on this one. Nevertheless, quiet operation is definitively a design criterion and the fan should be temperature controlled.

User interaction should be through a digital interface: we’ll want a nice display to show what’s what, and the user should be able to set the current using a fully-fledged 10-digit keypad. I guess this means microprocessor control.

The EDL will be used to test power supplies so it would be nice if it could be programmed in some way. At the very least, it should be able to modulate the load using both square and sine waves. But instead of going overboard here I believe that a simple BNC connection, hooked up to my function generator, could be used to inject a signal which could then be used to drive the load.

Then, we’ll need some kind of reverse input and short-circuit protection. We should also implement a flexible low-voltage cut-off functionality to protect rechargeable batteries during battery tests. The low-voltage threshold should be user-programmable.

The whole thing will sit on my bench so it should come in a nice, aluminum casing.

Let’s summarize:

Maximum load voltage 30 V
Maximum load current 5 A
Maximum power dissipation 150 W
Resolution 1 mA
Transient response < 10 ms
Quiet operation
Microprocessor controlled
Keypad for data entry
External control with function generator
Reverse input protection
User-programmable low-voltage cutoff
Flashy enclosure

This is a big project, so let’s take it one bit at a time.

First of all, we’ll have a look at how this thing works. We’ll start in an ideal world where all of our components have ideal properties and things like oscillation etc. don’t exist. We’ll worry about those problems later.

Theory of operation

An electronic dummy load sinks current in a controlled, user-defined way. Since you can’t control something if you don’t know what it is, we’re going to look into how we’re going to measure current first.

Fortunately, this is not very complicated. Thanks to Ohm’s law we know that the current through a resistor is the voltage across said resistor divided by its resistance :

I = \frac{V}{R}

Let’s call this resistor our sense resistor (Rs), and suppose its resistance is 1 Ω. If we measure a voltage drop of 3 volts across Rs it follows that 3 amps flow through it. This works in reverse, too: if we want a current of 3 amps through Rs we need to ensure that there is a voltage drop of 3 volts across Rs. Easy!

We now know how to measure the current we’re sinking. Next, we need a way to control it.

A transistor will regulate the current flow through the sense resistor. We’ll go for a FET. Why not choose a binary junction transistor, you ask? First, FETs are less noisy than BJTs, which always helps in a test & measurement environment. Then, they have better thermal stability; and finally, FETs scale better than BJTs, and since we might need a few power stages due to the high power dissipation we specced, that’s one less problem to deal with. (Don’t get the wrong impression, BJTs do have their raison d’être, just not in power stages of electronic loads.)

Finally, an operational amplifier, configured with a negative feedback loop, will regulate the amount of current that the transistor will let through. This is how it works:

A bare-bones current load

We apply a programming voltage (Vprog) to the op-amp’s non-inverting input. The op-amp wants to see an identical voltage on its inverting input, so it starts to drive its output which is connected to the FET’s gate. Through this mechanism, the op-amp will regulate the FET’s drain current in such a way that the voltage at the junction between Rsense and the op-amps inverting input is equal to the programming voltage, giving us the current flow we want :

I = \frac{V_{prog}}{R_{sense}}

Bingo, we have a programmable load!

The beauty of this configuration is that – due to the negative feedback – the whole system is pretty much self-contained and we don’t need to worry about anything.

So there’s your basic design. Of course we will have to deal with amplifier gain, loop oscillation, gate inductance and other little surprises (I lied, we do need to worry about this stuff), but that’ll come later.

Circuit simulation

Let’s simulate the proposed circuit to get a feel for it. I like to use LTspice for these kinds of experiments: it’s not exactly intuitive to use but very powerful and for this kind of work it’s almost perfect. And it’s free – what more can you ask for? If you want to follow my experiments, you can download the LTspice schematic here. (And don’t worry about components yet, these are for illustrative purposes only. We’ll pick the right components soon.)

Simulated circuit

First we’ll run a simple transient analysis of the circuit’s behavior, set up like so :

  • V1 is set to produce a 5 Vpp sine with an offset of 2.5 V (we don’t want it to turn negative).
  • V2 is the source that we want to draw current from. It’s set to 10 volts DC.
  • Rsense is set to 1 Ω, just to make the calculations easier.

Transient analysis: current follows nicely!

The green plot is the programming voltage, measured at the op-amp’s non-inverting input. It’s just V1’s output, if you like.

The red plot is the current flowing through Rsense. As you can see, it follows the programming voltage quite nicely, with a very nice linear relationship between the two. Apply 1 volt, you get 1 amp. Apply 5 volts, you get 5 amps. Just what we want.

Let’s check out the operating limits of our circuit. In the next simulation, things start to get a bit more interesting. I used a voltage ramp as programming voltage in order to see when the FET starts to conduct and what that does to the load. As you can see, there is a region where the current does not follow the programming voltage (mind the time base that has changed from the last plot). One would think that this is due to the fact that the FET’s gate threshold voltage Vgs(th) has not been reached yet and is therefore completely turned off. But this is only a symptom. Considering the op-amp’s output (the pink plot) we can see that the real cause of this delay is the op-amp’s limited slew-rate which is, in turn, limited by its internal compensation capacitor. Since this delay is intrinsic to the amplifier’s internal workings there’s nothing we can do about it, besides picking an op-amp with a faster slew-rate. In any case this is something we should measure on a live circuit to get the real picture.

Effects of the op-amps internal compensation network

Next, I wanted to brutalize the circuit a bit. This time, the programming signal is a 5 Vpp 1 kHz square wave. The resulting plot shows that there is considerable overshoot on the rising edge of the programming signal. This, also, is due to the op-amp’s compensation capacitor which forms an RC circuit with the rest of the amplification circuit and results in the settling waveform we can see on the zoomed-in portion of the plot. We’ll have to check on our live prototype if this problem is indeed present with “real” components.

Square wave mayhem

Ringing during op-amp settling

Finally, let’s have a look at our circuit’s compliance: the way the current draw follows the programming voltage. For that test, I changed Vprog back to DC and stepped it from 0 to 10 V in 1 volt steps. I also told LTspice that I wanted to cold-start the supplies in order to see the startup behaviour of the circuit (pretty much useless in this context, but it gives a nicer plot). As you can see the current follows nicely until we reach the 8 A point: here the current does not follow. This is due to the MOSFET’s Vgs(th) parameter: Vgs(th) is the minimum voltage difference between gate and source for the transistor to turn on. Since our simulated op-amp’s maximum output voltage is around 10 V, the MOSFET’s source voltage cannot exceed 8 V, and we’re limited to 8 A of current.

Compliance

In any case, these problems (slow turn-on, ringing during settling time, Vgs(th)-limited output) do not seem too bad – at least on paper. But, as they say, the proof is in the pudding. Which is why we need to build a small prototype: something we’ll be discussing in the next installment of this series.

This is part one of a series of articles on the design and construction of an electronic dummy load. To see all the articles at a glance, click on the “DC Load” tag in the tag cloud.