It’s prototyping time !

We will keep it simple: we’ll restrict ourselves to the basic schematic we proposed in the first part of this series, and we won’t worry too much about which specific op-amp and transistor to use. We’ll use whatever parts we find in the bin, after all this is about proving a concept. Once we get it working, we’ll hook the circuit up to the oscilloscope and have a look at what’s going on on the inside. Should be fun, let’s go!

# Our first prototype

This is it. As you can see, there’s not much to it: an op-amp (a run-of-the-mill LM324 which really is 4 separate op-amps in a single IC), a MOSFET (IRF510, again, nothing fancy), a 1 Ω high-power resistor standing in as Rsense, a few support resistors, and a handfull of patching wires.

Prototype schematic

The MOSFET’s drain is connected to a power supply which will provide the current for our tests. The PSU’s voltage is set to 10 volts, with a current limit set at 1.2 A. Its source is connected to the sense resistor and the op-amp’s inverting input.

I chose a 10 W high-power resistor as sense resistor because it will have to take all the current we’re going to source. A regular axial resistor is only specced up to 1/4 W, any more and it goes up in flames. Spectacular, certainly – but not what we want. This wire-wound one is enclosed in an aluminum chassis which doubles as heat sink and it can easily cope with up to 10 W of power.

The op-amp’s non-inverting input is connected to a function generator which will provide the programming voltage. The inverting input is connected to the sense resistor through a 1k resistor which will help limit oscillation and protect the op-amp’s input from eventual current spikes and artifacts comming from a misbehaving MOSFET. The same goes for the op-amp’s output which is connected through a 100 Ω resistor to the transistor’s gate terminal. This resistor will dampen down any ringing oscillations caused by lead inductance and gate capacitance which can otherwise exceed the maximum voltage allowed on the gate.

And in case you’re wondering, the op-amp is wired up in single-supply mode: V- is connected to circuit ground.

Function generator busy providing programming voltage

After turning on the PSU and enabling the function generator’s output, we can see that the circuit works as expected. With the programming voltage set to 1 V we measure a current draw of (approximately) 1A. Change the programming voltage and the current changes, too. Our circuit works. Cool!

Note: As you can see from the pictures we need to apply around 1.07 V to get a current draw of 1 A. This discrepancy is due to tolerances in our components – the high-power resistor for example has a tolerance of 1% which easily explains the difference we’re seeing. Since we’re planning on controlling this thing through a microcontroller we’ll be able to compensate for these component imperfections in the firmware.

1A !

So we’ve established that the circuit works. Let’s hook it to the scope and see what’s what :

CH1: Vprog, CH2: Rsense

Channel 1 is connected to the op-amp’s non-inverting input, and channel 2 is connected between the MOSFET’s source pin and Rsense. As you can see, the applied sine is present at Rsense, meaning that our current draw follows the programming voltage. There is not too much distortion, which is a good sign.

CH2: Rsense

On this zoomed-in plot we can see that our circuit is having a bit of a problem when the programming voltage nears GND: the start of the following sine cycle seems delayed, flattening out the sine wave’s trough. (Note how messed up the signal is, this is due to – yup – the breadboard.) We can investigate this problem further by applying a ramp as Vprog and focus on the op-amp’s output:

CH1: Vprog; CH2: Rsense, CH3: op-amp out

Here channels 3 is connected to the op-amp’s output. We can clearly see that our circuit has difficulties following a programming signal that’s below a certain voltage. I suspect this to be due to the LM324’s input voltage offset (3 mV max) and / or its input bias current (100 nA max).

CH1: Vprog; CH2: Rsense, CH3: op-amp out

Here we’re feeding a 1 kHz square wave to our circuit. As you can see, the simulation we ran in the first part of this series was right on the money: we’re seeing a bit of overshoot on the rising edge of the MOSFET’s source pin.

CH1: Vprog; CH2: Rsense, CH3: op-amp out

This is the same plot as before, only zoomed in on the rising edge of our programming signal (and some heavy filtering to get rid of artifacts). The op-amp overshoots, then takes its time to settle down which results in ripples at the MOSFET’s output. This has the potential to grow into fully fledged oscillation if not taken care of, especially at higher currents and frequencies. In our production circuit we will need to slow down the feedback loop to eliminate any possibility of phase reversal and thus oscillation.

# MOSFET selection

We need a MOSFET that works good in the linear region. The linear region of a MOSFET is the operating condition where the drain current Ids is mostly independent of the drain to source voltage Vds for any given gate to source voltage Vgs. In other words, in this operating region the drain current depends directly on the gate to source voltage.

With the advent of digital logic most semiconductor manufacturers are concentrating their efforts on improving their MOSFETs’ switching characteristics; which basically means that they try to lower the MOSFET’s on-resistance Rds(on) as much as possible. Sadly, lower Rds(on) means higher zero temperature coefficient (ZTC, this is the amount of Vgs below which the MOSFET is thermally instable). This is a bad thing for linear operation, because a higher ZTC means more derating of the safe operating area (SOA). See this application note for an excellent introduction to SOA derating and on how most of the existing datasheets have it wrong.

In any case; Rds(on) is totally irrelevant when using a MOSFET in linear mode. This means that we need to find a MOSFET for which 2.5 A of drain current at 30 V of drain to source voltage falls into the limits of its safe operating area. (Why not 5 A? We’ll see shortly that we need to use at least 2 MOSFETs in order to keep the temperature in check.)

The IRFP250 seems to fit the bill. Why this one? It’s used by Maynuo for their loads, and I figured that if it’s good enough for them it should be good enough for me!

# Thermal management

After deciding on the IRFP250, we’ll need to talk about thermal management. I know it’s not the most exciting topic, but it has to be addressed sometime and now is as good a time as any.

Per our specifications, our appliance will have to dissipate 150 W of power at maximum load. All of which will be transformed into heat. That heat has to go somewhere: we need to get it away from the MOSFET’s die. For this, we will use a heat sink. I like Ohmite’s C40 heat sink system a lot: you can put two of these back-to-back, hook a fan on one end and voilà you have a very efficient way of transporting heat away from your sensitive stuff. It even comes with convenient holding clips for TO-220 and TO-247 packages, so drilling holes into the aluminum body has become a thing of the past. Neat!

But before we get too excited about it, let’s crunch some numbers first.

### Heat sink calculations

According to the datasheet, the maximum junction temperature (Tj) of the IRFP250 is 150 °C. Let’s suppose that the ambient temperature (Tamb) in our lab is 25 °C. This leaves 125 °C of heat the MOSFET may produce before going up in flames (literally!) :

$T_{available} = T_{j} - T_{amb} = 150 ^{\circ}C - 25 ^{\circ}C = 125 ^{\circ}C$

Taking into consideration that our load will dissipate up to 150 W, the whole system must not exceed a thermal resistance of 0.83 °C/W :

$R_{TH_{max}} = \frac{T_{available}}{Power} = \frac{125 ^{\circ}C}{150 W} = 0.83 ^{\circ}C/W$

The total thermal resistance of our system consists of three elements:

• the junction-to-case resistance: R_THjc. According to the IRFP250’s datasheet, this is 0.65 °C/W ;
• the case-to-sink resistance: R_THcs. According to the datasheet, this is 0.24 °C/W ;
• the heat sink-fan-combo’s thermal resistance: R_THsink. Which we don’t know (yet).

$R_{TH_{system}} = R_{THjc} + R_{THcs} + R_{THsink}$

If you’ve been paying attention, you noticed that we’re already exceeding the maximum allowed thermal resistance by 0.06 °C/W with just R_THjc and R_THcs. This tells us that, at the set parameters, a single MOSFET will not be enough to dissipate all the heat. Bad news.

What can we do? Use more than one transistor, of course! Let’s go with two. If we balance them, each MOSFET will have half the total load to deal with: 75 W. Using the same formulas as above, this configuration gives us a maximum allowed thermal resistance of 1.67 °C/W.

$R_{TH_{max}} = \frac{T_{available}}{Power} = \frac{125 ^{\circ}C}{75 W} = 1.67 ^{\circ}C/W$

Subtracting the junction-to-case and case-to-think thermal resistances, this leaves us with a maximum of 0.78 °C/W for our heatsink :

$R_{THsink} <= R_{TH_{max}} - R_{THjc} + R_{THcs}$

$R_{THsink} <= 1.67 ^{\circ}C/W - 0.65 ^{\circ}C/W - 0.24 ^{\circ}C/W$

$R_{THsink} <= 0.78 ^{\circ}C/W$

So far, so good. Unfortunately, the heat sink’s datasheet does not specify its thermal resistance. But we can calculate it, approximately, using this nifty calculator. According to this simulation the C40 heat sink has – if cooled by a fan producing an airflow of about 6 cubic feet per minute – a thermal resistance of less than 0.55 °C/W. This is below our calculated limit, so we’re good. Conclusion: To stay within specifications the power stage will need to contain at least two MOSFETs and the heat sink will need a fan with a maximum air flow of 6 cubic feet per minute.

Just for kicks, let’s calculate how much power we could dissipate per transistor with this heat sink:

$P_{max} = \frac{T_{j} - T_{ambient}}{R_{THjc} + R_{THcs} + R_{THsink}}$

$P_{max} = 86.8 W$

Any more, and the junction gets too hot.

### Variable fan speed

The specifications call for quiet operation, which means that the appliance should try its best to keep fan noise down.

Here is a nice circuit: the error signal from a bridge, one leg of which is a negative temperature coefficient thermistor, is integrated by an op-amp. With the component values shown, the temperature setpoint is about 60 °C above which the integrator’s output is driven positive, turning the fan speed up. When the temperature falls, the integrator’s output is driven negative, slowing down the fan.

Proportional fan control

In order to limit feedback hunting, the integrator’s time constant (R33C28) should be chosen longer than the thermal time constant expected from the heat sink.

# Double whopper

The calculations above showed us that we need at least two MOSFETs to reach the power levels we specified. Putting them in parallel is not a good idea, simply because we’re too cheap to use matched transistors. Because of tiny imperfections during manufacturing non-matched transistors would not share the load equally, leading to thermal hotspots on one of the two. The one with the hotspot would see its drain-to-source voltage augment with respect to the other (the IRFP250 has a Vds temperature coefficient of 0.27 V/°C), further unbalancing the pair and making the hotter one even hotter. Rince, repeat, until you got thermal runaway. It is true that you can parallelize MOSFETs easier than BJTs, even without ballast resistors (but only in switching applications!); but since we’re trying to build a semi-precise measurement instrument here we’d like to keep things easy and clean. So we need another approach.

We’re going to duplicate the whole stage. Regulating op-amp and sense resistor included.

This way, each MOSFET gets regulated by its own op-amp, and each op-amp has its dedicated source of measurement for the feedback loop, which results in much better load balancing. Additionally, this configuration has better transient response than trying to drive multiple MOSFETs with a single op-amp: the gate of a FET is capacitive (total gate charge, Qg) and putting them in parallel makes it hard for a puny op-amp to drive them. If we give each MOSFET its dedicated op-amp, this us much less of a problem.

Of course we’ll have to do something about the programming voltage: returning to the chapter on the theory of operation; if we apply one volt of programming voltage at the circuit’s input, it is now fed to two op-amps controlling two FETs. So we’re in fact sourcing two amps – but we only want one. We’re going to need to divide the programming voltage by a factor of 2, and we’ll use a resistive divider for that.

Doubled-up power stage

Now it’s time to pick an op-amp. But before we can do that, we’ll need to take off our rose-colored glasses and look at the not-so-pretty properties of the components we’d like to use. We’ll do that in the next installment of this series: we’re going to talk about feedback oscillation, op-amp voltage offset and input bias current, gate inductance and other niceties that will give us a hard time.

And we’ll pick an op-amp.

Promised.

This is part two of a series of articles on the design and construction of an electronic dummy load. To see all the articles at a glance, click on the “DC Load” tag in the tag cloud.